To satisfy the demand for large scale digital integrated circuits, the semiconductor industry has developed three basic approaches. These include standard, off the shelf circuits; custom circuits; and gate arrays. The standard, off the shelf circuit provides the lowest cost option due to the quantities manufactured, but are limited in providing the flexibility for the circuit desired. The custom circuit is cost limiting unless the number of circuits desired is large. The gate array involves a standard array of a large number of gate circuits diffused into a chip. The metallization pattern converting these gate circuits into functional custom circuits is processed according to the customer's requirement.
Complex gate arrays may have several gates combined within a cell that performs a higher level logic function than a basic gate. These complex arrays have logic simulations directly implemented within the basic cell structure rather than formed by interconnecting logic gates. Each cell contains a number of unconnected transistors and resistors. A metallization interconnecting pattern transforms the interconnected transistors and resistors within each cell into Small Scale Integrated (SSI) logic functions, which take the form of standard logic elements such as dual type "D" flip-flops, dual full adders, quad latches, and many other predefined functions. These cells are also interconnected by the metallization to form the desired LSI design.
A typical complex gate array comprises at least a plurality of cells located in an inner portion of the IC, input/output pads and power pads around the periphery of the IC, and a regulator at each of the four corners of the IC for providing a current source voltage. These complex gate arrays perform a multitude of functions whenever the proper input signals are applied. However, when the gate array, or a portion of the gate array, is not being used, current is still required to keep the unused portion powered, resulting in an unnecessarily high current requirement.
Thus, what is needed in a gate array IC device or a master slice Large Scale Integrated (LSI) device in which portions of the device may be powered down when not in use.